This is the major advantage of implicit pulse triggering scheme. This leads to the reduction of power consumption due to clock allocation tree (pcik-tree) and reduces the delay time. Implicit clock is given to the transistors P2&N2 which supplies the clock signal to latching section. By following the implicit pulse triggering scheme, the clock allocation section is incorporated into the first latching stage itself. This flip-flop is designed by the following approaches such as implicit pulse triggering, dual edge clocking, rejection of floating node problem and reducing the number of clocked loads. Implicit pulsed-Double Edge Triggered Flip-Flop (IP-DETFF) is proposed for low power clocking system.
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